1. Field of the Invention
The present invention relates to frequency multiplying circuitry for doubling or otherwise multiplying the frequency of an input signal.
2. Description of the Background Art
It is a common practice with frequency multiplying circuitry to use delay available with an integrator circuit. Specific conventional frequency multiplying circuitry includes one inverter for inverting the level of an input clock signal. The one inverter has its output connected to another inverter with a resistor. Between the resistor and the other inverter, a node is formed, between which and the ground a capacitor is connected. The other inverter has its output connected to one input of an exclusive OR (EOR) gate, which has another input terminal connected to receive the clock signal. As a result, the exclusive OR gate outputs a frequency that is equal to a multiple of the frequency of the clock signal.
When the clock signal goes high, the one inverter also brings its output high, which is in turn input to an integrator circuit made up of the resistor and capacitor. Consequently, a signal appearing on the node, i.e., the output of the integrator circuit drops from its high level with a preselected time constant. When the level of the input signal drops to a threshold voltage particular to the other inverter, the output of the other inverter goes high. The exclusive OR gate produces an exclusive OR made between the clock signal and the output of the other inverter. More specifically, the output of the exclusive OR gate goes high at the positive-going edge of the clock signal and then goes low on the elapse of a preselected delay time.
As stated above, the frequency multiplying circuitry outputs its high level twice during a single period of the clock signal, i.e., doubles the frequency of the input clock signal.
The conventional frequency multiplying circuitry described above has the following problem left unsolved. The duration of the high level of the multiplied output signal is dependent upon the time constant of the integrator circuit and the threshold voltage of the other inverter. As a result, the duty ratio of the output signal varies due to the fluctuation of the frequency of the clock signal and that of power supply voltage. This causes successive logical circuitry controlled by the output signal of the frequency multiplying circuit to malfunction. It is to be noted that the above-mentioned duty ratio refers to the ratio of the duration of the high level to the single period of the clock signal.
It is an object of the present invention to provide frequency multiplying circuitry whose duty ratio is little susceptible to the frequency of an input clock signal and power supply voltage.
In accordance with the present invention, frequency multiplying circuitry multiplies the frequency of an input signal having a first logical level and a second logical level, different from the first logical level, alternating with each other at a preselected period. The circuitry includes a first and a second charging and discharging circuit. The first charging and discharging circuit charges a first capacitance with a first time constant representative of a relaxation time, which is based on the transient response of an electric circuit, in response to the first logical level of the input signal and then discharges it with a second time constant smaller than the first time constant. The second charging and discharging circuit charges a second capacitance with the first time constant in response to the second logical level of the input signal and then discharges it with the second time constant in response to the first logical level of the input signal. An output circuit compares the output voltages of the first and second charging and discharging circuits with a reference voltage and raises the level of an output signal when either one of the two output voltages drops below the reference voltage. A controller controls the charging and discharging of the first and second charging and discharging circuits in response to the input signal and output signal.
Also, in accordance with the present invention, frequency multiplying circuit includes a first and a second charging and discharging circuit. The first charging and discharging circuit includes a pair of a first and a second selector and a pair of a third and a fourth selector operating complementarily to each other in response to control signals each having a particular level different from each other. A first capacitance intervenes between a first signal line connecting the first and second selectors and a second signal line connecting the third and fourth selectors. A feed potential line applies power supply voltage to the first selector while a reference potential line applies a first reference potential to the third selector. A first resistor intervenes between the first reference potential terminal of the second selector and a second reference potential, e.g. ground. Likewise, a second resistor intervenes between a second reference potential terminal of the fourth selector and the second reference potential and has higher resistance than the first resistor. The first and fourth selectors each become active when the respective control signal is in a first logical level. On the other hand, the second and third selectors each become active when the respective control signal is in a second logical level different from the first logical level. The second charging and discharging circuit includes a pair of a fifth and a sixth selector and a pair of a seventh and an eighth selector also operating complementarily to each other in response to control signals each having a particular level different from each other. A second capacitance circuit intervenes between a third signal line connecting the fifth and sixth selectors and a fourth signal line connecting the seventh and eighth selectors. A feed potential line applies the power supply voltage to the fifth selector while a reference potential line applies the first reference potential to the seventh selector. A third resistor intervenes between the third reference potential terminal of the sixth selector and the second reference potential. Likewise, a fourth resistor intervenes between the fourth reference potential terminal of the eighth selector and the second reference potential and has higher resistance than the third resistor. The fifth and eighth selectors each become active when the respective control signal is in a first logical level while the sixth and seventh selectors each become active when the respective control signal is in a second logical level. An output circuit compares voltages output from the first and second charging and discharging circuits with the first reference voltage and outputs its high level as an output signal when either one of the two voltages drops below the reference voltage. A controller feeds the control signals to the first and second charging and discharging circuits in response to the input signal and output signal.